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THS7303PWG4 Datasheet(PDF) 8 Page - Texas Instruments |
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THS7303PWG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 43 page www.ti.com TIMING REQUIREMENTS (1) tw(H) tw(L) tr tf tsu(1) th(1) SCL SDA tsu(2) th(2) tsu(3) t(buf) SCL SDA Start Condition Stop Condition THS7303 SLOS479 – OCTOBER 2005 V S+ = 2.7 V to 5 V STANDARD MODE FAST MODE PARAMETER UNIT MIN MAX MIN MAX fSCL Clock frequency, SCL 0 100 0 400 kHz tw(H) Pulse duration, SCL high 4 0.6 µs tw(L) Pulse duration, SCL low 4.7 1.3 µs tr Rise time, SCL and SDA 1000 300 ns tf Fall time, SCL and SDA 300 300 ns tsu(1) Setup time, SDA to SCL 250 100 ns th(1) Hold time, SCL to SDA 0 0 ns t(buf) Bus free time between stop and start conditions 4.7 1.3 µs tsu(2) Setup time, SCL to start condition 4.7 0.6 µs th(2) Hold time, start condition to SCL 4 0.6 µs tsu(3) Setup time, SCL to stop condition 4 0.6 µs Cb Capacitive load for each bus line 400 400 pF (1) The THS7303 I2C address = 01011(A1)(A0)(R/W). See the application information section for more information. Figure 2. SCL and SDA Timing Figure 3. Start and Stop Conditions 8 |
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