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GS9021 Datasheet(PDF) 10 Page - Gennum Corporation |
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GS9021 Datasheet(HTML) 10 Page - Gennum Corporation |
10 / 26 page 521 - 65 - 05 10 3.3 CRC Calculation And Updating Since the device has the potential of modifying the full-field and active picture data with features like ITU-R-601 clipping and TRS insertion, the full field and active picture CRC values must be calculated for both the incoming and outgoing data streams. The calculated CRC values based on the incoming data stream are used for comparison with the embedded CRC values. However, the calculated CRC values based on the outgoing data stream are the ones inserted into the data stream. As a result, the CRC values in the outgoing data stream correctly reflect the contents of the outgoing data stream. The INCOMING FF and AP CRC values for the Full Field (FF) and Active Picture (AP) regions can be read from the HOSTIF read table. Similarly, the OUTGOING (calculated) FF and AP CRC values for the Full Field and Active Picture regions can be read from the HOSTIF read table. 3.4 Validity Bit The VALIDITY (V) bits (as per SMPTE 165) present in the incoming EDH packet are used to indicate whether the CRC values are valid or invalid. If the V bit is HIGH, the CRC value is considered valid. In this case, the incoming CRC value is compared with the calculated CRC value to identify errors. If the V bit is LOW, the incoming CRC is invalid and a CRC comparison is not performed. If the device receives an EDH packet with the V bit set LOW it behaves as follows: 1. EDH = 0 (Not asserted for an invalid CRC) 2. EDA = EDAin "OR" EDHin (EDA calculated as usual) 3. A new calculated CRC value replaces the invalid one in the output EDH packet 4. The V bit will be set HIGH in the output EDH packet 5. Depending on whether one or both of FFV or APV is low, the Unknown Error Status (UES) flag corresponding to either FF or AP or both, is set HIGH in the output data. (No CRC check could be performed, so the data may or may not contain errors). The incoming V bits for the Full Field and Active Picture regions are available in the HOSTIF read table as FFV and APV, respectively. Outgoing full field (FFV) and active picture (APV) validity bits are set HIGH unless explicitly over-written through the HOSTIF write table or the flag port. 3.5 Ancillary Checksum Verification For each received ANC packet in the incoming data, the device compares the calculated checksum value to the embedded checksum for that ANC packet. If the checksum values do not match for any ANC packets within a field, an error is reported via the ANC EDH flag in the EDH packet. In addition, if the ANC_CHKSM input pin or HOSTIF write table bit is asserted HIGH, the ancillary checksum correction block is enabled and the checksum in the ANC packet is replaced with the calculated one. This update is required to prevent the ANC data error from being flagged at every downstream EDH chip. When implementing applications which use the EDH core (ie. BYPASS_EDH set LOW), the ANC_CHKSM function will indicate a downstream FF/AP EDH error when an illegal/ non-allowed (3FCH-3FFH) ANC_CHKSM input value is detected. As such, these values should not be present in the incoming data and the corresponding FF/AP EDH errors should not occur. However, if the user wishes to disable the ANC_CHKSM function, it can be deactivated by setting both the ANC_CHSKM pin and the ANC_CHKSM host interface bit LOW. If the chip is receiving ANC EDH flag information through the flag port or the HOSTIF, then the ANC EDH flag generated by the ancillary checksum verification block will be overwritten. However, the additional FF/AP EDH flag will still appear at the next downstream chip if an illegal checksum of 3FCH-3FFH was detected and the ANC_CHKSM function was enabled. If a checksum error is detected in the EDH packet itself, an additional separate error flag, EDH_CHKSM is set HIGH in the HOSTIF read table. PIN LOGIC OPR HOST BIT INCOMING FF CRC OUTGOING FF CRC INCOMING AP CRC OUTGOING AP CRC PIN LOGIC OPR HOST BIT FFV APV PIN LOGIC OPR HOST BIT ANC_CHKSM EDH_CHKSM |
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