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BQ2058TRSN Datasheet(PDF) 2 Page - Texas Instruments |
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BQ2058TRSN Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 18 page  Pin Descriptions CHG Charge control output This open-drain output controls the charge path to the battery pack. Charging is allowed when high. CTL Pack disable input When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal opera- tion, the CTL pin is low. VSS Low potential input CSL Overcurrent sense low-side input This input is connected between the low-side discharge FET (or sense resistor) and BAT2N to enable overcurrent sensing in the battery pack’s ground path. BAT2N Battery 2 negative inputs (3 pins) These pins are connected to the negative termi- nal of the cell designated BAT2 in Figure 2. BAT1N Battery 1 negative input This input is connected to the negative termi- nal of the cell designated BAT1 in Figure 2. DSG Discharge control output This push-pull output controls the discharge path to the battery pack. Discharge is al- lowed when high. UVD Undervoltage delay input This input uses an external capacitor to VCC to set the undervoltage delay timing. OVD Overvoltage delay input This input uses an external capacitor to VCC to set the overvoltage delay timing. OCD Overcurrent delay input This input uses an external capacitor to VCC to set the overcurrent delay timing. VCC High potential inputs (2 pins) CSH Overcurrent sense high-side input This input is connected between the high-side discharge FET (or sense resistor) and BAT1P to enable overcurrent sense in the battery pack’s positive supply path. BAT1P Battery 1 positive input This input is connected to the positive terminal of the cell designated BAT1 in Figure 2. 2 July 1997 bq2058T |
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