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PCI1031PDV Datasheet(PDF) 8 Page - Texas Instruments |
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PCI1031PDV Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 100 page  PCI1031 PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) PCI interface control TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION DEVSEL 197 I/O Device select. As a PCI target, the PCI1031 asserts DEVSEL to claim the current cycle. As a PCI master, the PCI1031 monitors DEVSEL until a target responds or a time-out occurs. FRAME 193 I/O Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an access. FRAME is low (asserted) to indicate that a bus transaction is beginning. While FRAME is asserted, data transfers continue. When FRAME is sampled high (deasserted), the transaction is in the final data phase. GNT 168 I Grant. GNT is driven by the PCI arbiter to grant the PCI1031 access to the PCI bus after the current data transaction is complete. If distributed DMA is not implemented, GNT must be pulled high with a 43-k Ω resistor. IDSEL 182 I Initialization device select. IDSEL selects the PCI1031 during configuration accesses. IDSEL can be connected to one of the upper 24 PCI address lines. IRDY 195 I/O Initiator ready. IRDY indicates the bus master’s ability to complete the current data phase of the transaction. IRDY is used with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled low (asserted). During a write, IRDY indicates that valid data is present on AD31– AD0. During a read, IRDY indicates that the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are low (asserted) at the same time. IRDY is an output when the PCI1031 is the PCI bus master and an input when the PCI bus is the target. PERR 199 I/O Parity error. PERR is driven by the PCI target during a write to indicate that a data parity error has been detected. REQ 169 O Request. REQ asserted by the PCI1031 to request access to the PCI bus as a master. SERR 200 O System error. SERR pulsed from the PCI1031 indicates an address parity error has occurred. If SERR is not used, it must be pulled high with a 43-k Ω resistor. STOP 198 I/O Stop. STOP is driven by the current PCI target to request the master to stop the current transaction. TRDY 196 I/O Target ready. TRDY indicates the ability of the PCI1031 to complete the current data phase of the transaction. TRDY is used with IRDY. A data phase is completed on any clock where both TRDY and IRDY are sampled asserted. During a read, TRDY indicates that valid data is present on AD31– AD0. During a write, TRDY indicates that the PCI1031 is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted together. TRDY is an output when the PCI1031 is the PCI target and an input when the PCI1031 is the PCI bus master. power supply TERMINAL FUNCTION NAME NO. FUNCTION GND 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207 Device ground terminals VCC 7, 31, 64, 86, 113, 143, 164, 175, 187, 201 Power-supply terminals for core logic (3.3 V) VCCA 120 Power-supply terminal for PC Card A (5 V or 3.3 V) VCCB 38 Power-supply terminal for PC Card B (5 V or 3.3 V) VCCP 148, 172 Power-supply terminals for PCI interface (5 V or 3.3 V) |
Similar Part No. - PCI1031PDV |
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Similar Description - PCI1031PDV |
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