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P87C453EFLKA Datasheet(PDF) 7 Page - NXP Semiconductors |
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P87C453EFLKA Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 23 page Philips Semiconductors Preliminary specification 80C453/83C453/87C453 CMOS single-chip 8-bit microcontrollers 1996 Aug 15 3-317 PX0 LSB MSB BIT SYMBOL FUNCTION IP.7 — Reserved. IP.6 POB Defines the Output Buffer Full interrupt (IOB) priority level. POB=1 programs it to the higher priority level. IP.5 PIB Defines the Input Buffer Full interrupt (IIB) priority level. PIB=1 programs it to the higher priority level. IP.4 PS Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level. IP.3 PT1 Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level. IP.2 PX1 Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level. IP.1 PT0 Enables or disables the Timer 0 interrupt priority level. PT0=1 programs it to the higher prior- ity level. IP.0 PX0 Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level. SU00564 PT0 PX1 PT1 PS PIB POB — Figure 3. 8XC453 Interrupt Priority (IP) Register IDL PCON (87H) BIT SYMBOL FUNCTION PCON.7 SMOD1 Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the Serial Port is used in modes 1, 2, or 3. PCON.6 SMOD0 If set to 1, SCON.7 will be the Framing Error bit (FE). If PCON.6 is cleared, SCON.7 will be SM0. PCON.5 — Reserved. PCON.4 POF Power Off Flag is set during power on of VCC. If then cleared by software, it can be used to determine if a warm start has occurred. PCON.3 GF1 General-purpose flag bit. PCON.2 GF0 General-purpose flag bit. PCON.1 PD Power-Down bit. Setting this bit activates power-down mode. It can only be set if input EW is high. PCON.0 IDL Idle mode bit. Setting this bit activates the idle mode. If logic 1s are written to PD and IDL at the same time, PD takes precedence. SU00565 PD GF0 GF1 POF — SMOD2 SMOD1 0 1 2 3 4 5 6 7 Figure 4. Power Control Register (PCON) |
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