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IC42S8200-7T Datasheet(PDF) 1 Page - Integrated Circuit Solution Inc |
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IC42S8200-7T Datasheet(HTML) 1 Page - Integrated Circuit Solution Inc |
1 / 76 page ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. .EATURES Clock frequency: 166, 143, 125, 100 MHz .ully synchronous; all signals referenced to a positive clock edge Two banks can be operated simultaneously and independently Dual internal bank controlled by A11 (bank select) Single 3.3V power supply LVTTL interface Programmable burst length (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto refresh, self refresh 4096 refresh cycles every 128 ms Random column address every clock cycle Programmable +)5 latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Package 400mil 44-pin TSOP-2 DESCRIPTION 1+51's 16Mb Synchronous DRAM IC42S8200 is organized as a 1Meg x 8-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. 1+" 5& 1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM PIN CON.IGURATIONS 44-Pin TSOP-2 PIN DESCRIPTIONS A0-A11 Address Input A0-A10 Row Address Input A11 Bank Select Address A0-A8 Column Address Input I/O0 to I/O7 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command WE Write Enable DQM Input/Output Mask Vcc Power GND Ground VccQ Power Supply for I/O Pin GNDQ Ground for I/O Pin NC No Connection Integrated Circuit Solution Inc. 1 DR018-0A 07/10/2001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC I/O0 GNDQ I/O1 VccQ I/O2 GNDQ I/O3 VccQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC GND I/O7 GNDQ I/O6 VCCQ I/O5 GNDQ I/O4 VCCQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND |
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