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TPS73018DBVTG4 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS73018DBVTG4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 15 page www.ti.com APPLICATION INFORMATION TPS730xx GND EN NR IN OUT V IN V OUT V IN V OUT 2.2 µF 0.01 µF(1) 0.1 µF NOTE: (1) This capacitor is optional. External Capacitor Requirements Board Layout Recommendation to Improve PSRR and Noise Performance TPS730xx SBVS054E – NOVEMBER 2004 – REVISED AUGUST 2005 The TPS730xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA when the regulator is turned off. A typical application circuit is shown in Figure 16. Figure 16. Typical Application Circuit A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS730xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated or the device is located several inches from the power source. Like most low dropout regulators, the TPS730xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 2.2 µF. Any 2.2-µF or larger ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. If load current is not expected to exceed 100 mA, a 1.0-µF ceramic capacitor can be used. The internal voltage reference is a key source of noise in an LDO regulator. The TPS730xx has an NR pin which is connected to the voltage reference through a 250-k Ω internal resistor. The 250-kΩ internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1-µF to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the Functional Block Diagrams As an example, the TPS73018 exhibits only 23 µVRMS of output voltage noise using a 0.01-µF ceramic bypass capacitor and a 2.2-µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the NR pin that is created by the internal 250-k Ω resistor and external capacitor. To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. 7 |
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