C32025 Megafunction Datasheet
CAST, Inc.
May 2004
Page 3
Pin Description
Name
Type
Polarity/
Bus size
Description
clk
I
Rise
Master clock input
All internal synchronous circuits clock
clkout1
O
-
Master clock output (fclk/4)
When High it indicates internal quarter-phases Q3 and Q4
clkout2
O
-
Second clock output (fclk/4)
When High it indicates internal quarter-phases Q2 and Q3
rs_n
I
Low
Hardware reset input
Active for 2 cycles resets the device
mpmc
I
-
Microprocessor/microcomputer mode
When Low the internal ROM is mapped into program space
sync_n
I
Fall
Synchronization input
Forces the internal quarter-phase to Q1
hold_n
I
Low
Hold input
Forces processor to place the data & address buses and control lines
in the hi-Z state
holda_n
O
Low
Hold acknowledge output
Indicates that processor is in the hold mode
int0_n
int1_n
int2_n
I
I
I
Low/Fall
Low/Fall
Low/Fall
External interrupt inputs
External interrupt 0
External interrupt 1
External interrupt 2
iack_n
I
Low
Interrupt acknowledge
Indicates branching to the interrupt vector
ps_o
ds_o
is_o
O
O
O
Low
Low
Low
Program, data and I/O space select signals
ps_tri
ds_tri
is_tri
O
O
O
High
High
High
Select signals tri-state control
Enables external tri-state buffers
rw_o
O
-
Read/write output signal
Indicates external transfer direction. High means reading
rw_tri
O
H
Read/write tri-state control
Enables external tri-state buffer
strb_o
O
Low
Strobe signal
Low indicates an external bus cycle
strb_tri
O
High
Strobe tri-state control signal
Enables external tri-state buffer
ready
I
High
Data ready input
Indicates that external device is prepared for transfer to be
completed
bio_n
I
Low
Branch control input
When active the BIOZ branch occurs
br_n
O
Low
Bus request output
Asserted when the processor requires access to external global data
memory space
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