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ADIS16489 Datasheet(PDF) 35 Page - Analog Devices |
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ADIS16489 Datasheet(HTML) 35 Page - Analog Devices |
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35 / 40 page  Data Sheet ADIS16489 Rev. B | Page 35 of 40 The contents in the PAGE_ID register (see Table 196 and Table 197) contain the current page setting, and provide a control for selecting another page for SPI access. For example, set DIN = 0x8002 to select Page 2 for SPI-based user access. See Table 10 for the page assignments associated with each user accessible register. PART IDENTIFICATION NUMBERS (PART_ID1, PART_ID2, PART_ID3, PART_ID4) Table 198. PART_ID1 Register Definitions Page Addresses Default Access Flash Backup 0x04 0x20, 0x21 Not applicable R Not applicable Table 199. PART_ID1 Bit Definitions Bits Description [15:0] Part Identification 1 Table 200. PART_ID2 Register Definitions Page Addresses Default Access Flash Backup 0x04 0x22, 0x23 Not applicable R Not applicable Table 201. PART_ID2 Bit Definitions Bits Description [15:0] Part Identification 2 Table 202. PART_ID3 Register Definitions Page Addresses Default Access Flash Backup 0x04 0x24, 0x25 Not applicable R Not applicable Table 203. PART_ID3 Bit Definitions Bits Description [15:0] Part Identification 3 Table 204. PART_ID4 Register Definitions Page Addresses Default Access Flash Backup 0x04 0x26, 0x27 Not applicable R Not applicable Table 205. PART_ID4 Bit Definitions Bits Description [15:0] Part Identification 4 FIR FILTERS The ADIS16489 has four user configurable FIR filter banks. The sample rate of the FIR filters is identical to the inertial measurement unit (IMU) sample rate. Because decimation occurs after the FIR filters, the FIR sample rate is independent of the decimation rate and is not affected by the setting of the DEC_RATE register. If the user selects the internally generated sample clock (which is the default setting), the nominal IMU sample rate (and FIR sample rate) is 2460 SPS. If the user is supplying an external clock by setting Bit 7 of the FNCTIO_ CRTL register to 1 (see Table 152 and Table 153), the FIR sample rate is the same as the ADIS16489 sample rate. The user can individually configure and select one of the four FIR filter banks for each individual inertial sensor using the FILTR_ BNK_0 (see Table 166) and FILTR_BNK_1 (see Table 168) registers (see Figure 33). Each FIR filter bank (A, B, C, D) has 120 taps that consume two pages of memory. The coefficient associated with each tap in each filter bank has its own dedicated register that uses a 16-bit, twos complement format. The FIR filter has unity-gain when the sum of all of the coefficients is equal to 32,768. For filter designs that require fewer than 120 taps, ensure that the non-zero taps are in the lower-numbered coefficients and write 0x0000 to all unused taps to eliminate the latency associated with that particular tap. Page 5, Page 6 (PAGE_ID) Table 206. PAGE_ID Register Definition Page Addresses Default Access Flash Backup 0x05. 0x06, 0x00, 0x01 0x0000 R/W No Table 207. PAGE_ID Bit Assignments Bits Description [15:0] Page number, binary numerical format The contents in the PAGE_ID register (see Table 206 and Table 207) contain the current page setting, and provide a control for selecting another page for SPI access. For example, set DIN = 0x8002 to select Page 2 for SPI-based user access. See Table 10 for the page assignments associated with each user accessible register. FIR Filter Bank A (FIR_COEF_A000 to FIR_COEF_A119) Table 208. FIR Filter Bank A Memory Map Page PAGE_ID Addresses Register 5 0x05 0x00, 0x01 PAGE_ID 5 0x05 0x02 to 0x07 Not used 5 0x05 0x08, 0x09 FIR_COEF_A000 5 0x05 0x0A, 0x0B FIR_COEF_A001 5 0x05 0x0C to 0x7D FIR_COEF_A002 to FIR_COEF_A058 5 0x05 0x7E, 0x7F FIR_COEF_A059 6 0x06 0x00, 0x01 PAGE_ID 6 0x06 0x02 to 0x07 Not used 6 0x06 0x08, 0x09 FIR_COEF_A060 6 0x06 0x0A, 0x0B FIR_COEF_A061 6 0x06 0x0C to 0x7D FIR_COEF_A062 to FIR_COEF_A118 6 0x06 0x7E, 0x7F FIR_COEF_A119 Table 209 and Table 210 offer detailed register and bit definitions for one of the FIR coefficient registers in Bank A, FIR_COEF_ A071. Table 211 provides a configuration example, which sets this register to a decimal value of −169 (0xFF57). Table 209. FIR_COEF_A071 Register Definitions Page Addresses Default Access Flash Backup 0x06 0x1E, 0x1F Not applicable R/W Yes Table 210. FIR_COEF_A071 Bit Definitions Bits Description [15:0] FIR Bank A, Coefficient 71, twos complement |
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