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ADIS16489 Datasheet(PDF) 6 Page - Analog Devices |
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ADIS16489 Datasheet(HTML) 6 Page - Analog Devices |
6 / 40 page ![]() ADIS16489 Data Sheet Rev. B | Page 6 of 40 TIMING SPECIFICATIONS TC = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. Parameter Description Min1 Typ Max1 Unit fSCLK Serial clock 0.01 15 MHz tSTALL2 Stall period between data 2 µs tCLS Serial clock low period 31 ns tCHS Serial clock high period 31 ns t CS Chip select to clock edge 32 ns tDAV DOUT valid after SCLK edge 10 ns tDSU DIN setup time before SCLK rising edge 2 ns tDHD DIN hold time after SCLK rising edge 2 ns tDR, tDF DOUT rise/fall times, ≤100 pF loading 3 8 ns tDSOE CS assertion to data out active 0 11 ns tHD SCLK edge to data out invalid 0 ns tSFS Last SCLK edge to CS deassertion 32 ns tDSHI CS deassertion to data out high impedance 0 9 ns Data ready pulse width 11 15 µs t1 Input sync pulse width 5 µs t2 Input sync to data invalid 560 570 µs t3 Input sync period 417 µs 1 Guaranteed by design and characterization, but not tested in production. 2 See Table 3 for exceptions to the stall time rating. Register Specific Stall Times Table 3. Parameter Description Min1 Typ Max Unit STALL TIME FNCTIO_CTRL Configure DIOx functions 15 μs FILTR_BNK_0 Enable/select finite impulse response (FIR) filter banks 10 μs FILTR_BNK_1 Enable/select FIR filter banks 10 μs NULL_CNFG Configure autonull bias function 10 μs GLOB_CMD[1] Self test 12000 μs GLOB_CMD[2] Flash memory test 50000 μs GLOB_CMD[3] Flash memory update 375000 ms GLOB_CMD[6] Factory calibration restore 75000 sec GLOB_CMD[7] Software reset 120000 ms 1 Monitoring the data ready signal (see Table 153 for FNCTIO_CTRL configuration) for the return of regular pulsing can help minimize system wait times. |
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