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ADIS16489 Datasheet(PDF) 12 Page - Analog Devices

Part # ADIS16489
Description  Seven Degrees of Freedom Inertial Sensor
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
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ADIS16489 Datasheet(HTML) 12 Page - Analog Devices

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ADIS16489
Data Sheet
Rev. B | Page 12 of 40
R/W
R/W
A6
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CS
SCLK
DIN
DOUT
A6
A5
D13
D14
D15
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 13. SPI Communication Bit Sequence
SPI COMMUNICATION
Each SPI command and response is 16 bits in length and uses
the digital coding from Figure 13.
DEVICE CONFIGURATION
Each register contains 16 bits (two bytes). Bits[7:0] contain the
low byte, and Bits[15:8] contain the high byte of each register. Each
byte has its own unique address in the user register map (see
Table 10). Update the contents of a register by writing to its low
byte first and its high byte second. There are three parts to
coding a SPI command (see Figure 13), which writes a new byte
of data to a register: the write bit (R/W = 1), the address of the
byte, [A6:A0], and the new data for that location, [DC7:DC0].
Figure 14 provides a coding example for writing 0xFEDC to the
XG_BIAS_LOW register (see Table 109), assuming the
PAGE_ID register already equals 0x0002.
SCLK
CS
DIN
0x90DC
0x91FE
Figure 14. SPI Sequence for Writing 0xFEDC to XG_BIAS_LOW
Dual Memory Structure
The ADIS16489 uses a dual memory structure (see Figure 15) in
which the SRAM supports real-time operation and the flash
memory provides nonvolatile storage. During the start-up
process, the operating code, calibration coefficients, and user
register settings load from the flash memory into the SRAM to
support normal operation. The manual flash update command
(GLOB_CMD[3], see Table 151) provides a simple method for
saving user register values to the flash memory. Registers with the
flash backup feature are indicated by a yes in the flash backup
column of Table 10. This flash backup preserves these settings
for automatic recall during the next power-on or reset recovery
process.
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
MANUAL
FLASH
BACKUP
START-UP
RESET
VOLATILE
SRAM
SPI ACCESS
Figure 15. SRAM and Flash Memory Diagram
READING SENSOR DATA
The 16-bit command code (see Figure 13) for a read request on
the SPI has three parts: the read bit (R/W = 0), either address of
the register, [A6:A0], and eight don’t care bits, [DC7:DC0]. A
read command produces the registers contents on the DOUT
pin, during the following 16-bit communication cycle. Figure 16
provides an example that includes two register reads in succes-
sion. This example starts with DIN = 0x1A00, to request the
contents of the Z_GYRO_OUT register, and follows with 0x1800,
to request the contents of the Z_GYRO_LOW register (assuming
the PROD_ID register already equals 0x0000). This is an
example of full duplex operation in which the ADIS16489
receives a new request while transmitting the data response
from the prior request (see Figure 16).
DIN
DOUT
0x1A00
0x1800
NEXT
ADDRESS
Z_GYRO_OUT
Z_GYRO_LOW
Figure 16. SPI Read Example
Figure 17 provides an example of the four SPI signals when
reading the PROD_ID register (see Table 93) in a repeating
pattern. This pattern is helpful when troubleshooting the SPI
interface as it provides a clear expectation for all signals because
the register contents involved never change.
SCLK
CS
DIN
DOUT
DOUT = 0100 0000 0110 1001 = 0x4069 = 16,489 (PROD_ID)
DIN = 0111 1110 0000 0000 = 0x7E00
Figure 17. SPI Read Example, Second 16-Bit Sequence


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