 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ICE3DS01LG Datasheet(PDF) 10 Page - Infineon Technologies AG |
|
||||||||||||||||||||||||||||||
ICE3DS01LG Datasheet(HTML) 10 Page - Infineon Technologies AG |
|
|
10 / 27 page  F3 ICE3DS01L/LG Functional Description Version 2.0 10 15 May 2003 3.4 PWM Section Figure 7 PWM Section 3.4.1 Oscillator The oscillator generates a frequency f switch = 110kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of D max=0.72. 3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWM-Latch when initiating the external Power Switch conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator, the Current-Limit comparator or comparator C3. In case of resetting the driver is shut down immediately. 3.4.3 Gate Driver The Gate Driver is a fast totem pole gate drive which is designed to avoid cross conduction currents and which is equipped with a zener diode Z1 (see Figure 8) in order to improve the control of the Gate attached power transistors as well as to protect them against undesirable gate overvoltages. The Gate Driver is active low at voltages below the undervoltage lockout threshold V VCCoff. Figure 8 Gate Driver The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the external Power Switch threshold. This is achieved by a slope control of the rising edge at the driver’s output (see Figure 9). Figure 9 Gate Rising Slope Thus the leading switch on spike is minimized. When the external Power Switch is switched off, the falling shape of the driver is slowed down when reaching 2V to prevent an overshoot below ground. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. Oscillator Duty Cycle max Gate Driver 0.72 Clock & G9 1 G8 PWMSection FF1 R S Q Gate Soft Start Comparator PWM Comparator Current Limiting Comparator C3 Z1 VCC 1 PWM-Latch Gate t V Gate 5V C Load = 1nF ca. t = 130ns |
Similar Part No. - ICE3DS01LG |
|
Similar Description - ICE3DS01LG |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
