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UCC3882DW-1G4 Datasheet(PDF) 6 Page - Texas Instruments

Part # UCC3882DW-1G4
Description  AVERAGE CURRENT MODE SYNCHRONOUS CONTROLLER WITH 5-BIT DAC
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

UCC3882DW-1G4 Datasheet(HTML) 6 Page - Texas Instruments

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DAC INFORMATION
UCC3882/-1
SLUS294A – MARCH 1999 – REVISED OCTOBER 2005
VDRVLO: This pin supplies power to the low side
output and enables the GATELO output, forcing 0%
output
driver,
GATELO.
VDRVLO
is
typically
duty cycle on the power supply. This pin is also used
connected to a 12V source, but may be connected to
by the foldback current limiting circuitry to indicate
a 5V source for driving logic level MOSFETs. This pin
when the output voltage has been short circuited.
should be bypassed directly to PGND using a low
VSNS should be decoupled very closely to the IC
ESR capacitor.
with
a
capacitor
to
GND.
The
OV
and
UV
comparators’ hysteresis is typically 20mV, requiring
VIN: This pin supplies power to the chip. Connect
good layout and filtering techniques to insure that
VIN to a stable voltage source that is at least 10.8V
noise and ground-bounce do not inadvertently trip the
above GND. The GATEHI, GATELO and PWRGD
OV and UV comparators. It is recommended that an
outputs will be held low until VCC exceeds the upper
R-C filter set to approximately Fs/10 be used to filter
undervoltage lockout threshold. This pin should be
noise from the system output, where Fs is the
bypassed directly to GND.
oscillator frequency.
VFB: This pin is the inverting input to the error
amplifier. This input is connected to COMP through a
feedback network and to the power supply output
The
5-bit
Digital-to-Analog
Converter
(DAC)
is
through a resistor or a divider network.
programmed according to Table 1.The COMMAND
VREF: This pin provides an accurate 5V reference
voltage is always active as long as the UCC3882 VIN
and is internally short circuit current limited. VREF
pin is above the undervoltage lockout voltage. For the
powers the D/A Converter and also provides a
3882, the output gate drives GATEHI and GATELO
threshold voltage for the UVLO comparator. For best
are disabled at certain DAC codes, as shown in
reference stability, bypass VREF directly to GND with
Table 1. Disabling the gate drives disables the power
a low ESR, low ESL capacitor of at least 0.01
µF.
supply. For the 3882 -1, the GATEHI and GATELO
drives are enabled for all DAC codes. For a given
VSNS: This pin is connected to the system output
code, the power supply output regulates at the
voltage through a low pass R-C filter. When the
corresponding COMMAND voltage.
voltage on VSNS rises above or falls below the
COMMAND voltage by 9%, the PWRGD output is
driven low to reset the microprocessor. When the
voltage on VSNS rises above the COMMAND voltage
by 17.5%, the OVP comparator disables the GATEHI
Table 1. Programming the Command Voltage for the UCC3882
Digital Command
Command
GATEHI/GATELO
Digital Command
Command
GATEHI/GATELO
Voltage
Status
Voltage
Status
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
0
1
1
1
1
1.300
Note 1 ?
1
1
1
1
1
2.000
Note 1 ?
0
1
1
1
0
1.350
Note 1 ?
1
1
1
1
0
2.100
Enabled
0
1
1
0
1
1.400
Note 1 ?
1
1
1
0
1
2.200
Enabled
0
1
1
0
0
1.450
Note 1 ?
1
1
1
0
0
2.300
Enabled
0
1
0
1
1
1.500
Note 1 ?
1
1
0
1
1
2.400
Enabled
0
1
0
1
0
1.550
Note 1 ?
1
1
0
1
0
2.500
Enabled
0
1
0
0
1
1.600
Note 1 ?
1
1
0
0
1
2.600
Enabled
0
1
0
0
0
1.650
Note 1 ?
1
1
0
0
0
2.700
Enabled
0
0
1
1
1
1.700
Note 1 ?
1
0
1
1
1
2.800
Enabled
0
0
1
1
0
1.750
Note 1 ?
1
0
1
1
0
2.900
Enabled
0
0
1
0
1
1.800
Enabled
1
0
1
0
1
3.000
Enabled
0
0
1
0
0
1.850
Enabled
1
0
1
0
0
3.100
Enabled
0
0
0
1
1
1.900
Enabled
1
0
0
1
1
3.200
Enabled
0
0
0
1
0
1.950
Enabled
1
0
0
1
0
3.300
Enabled
0
0
0
0
1
2.000
Enabled
1
0
0
0
1
3.400
Enabled
0
0
0
0
0
2.050
Enabled
1
0
0
0
0
3.500
Enabled
6


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