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IDT7018L20PFI Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT7018L20PFI Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 17 page  10 IDT7018L High-Speed 64K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. Industrial Temperature: for specific speeds, packages and powers contact your sales office. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 7018L15 Com'l Only 7018L20 Com'l Only Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 15 ____ 20 ns tBDC BUSY Acce ss Time from Chip Enable High ____ 15 ____ 17 ns tAPS Arbitration Priority Set-up Time(2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 15 ____ 17 ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns BUSY TIMING (M/S=VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 30 ____ 45 ns tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 30 ns 4841 tbl 14 |
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