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BQ29330DBTG4 Datasheet(PDF) 3 Page - Texas Instruments |
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BQ29330DBTG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 26 page www.ti.com bq29330 SLUS673A – SEPTEMBER 2005 – REVISED DECEMBER 2005 TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME DBT NO. RHB NO. CELL– 1 28 Output of scaled value of the measured cell voltage. CELL+ 2 29 Output of scaled value of the measured cell voltage. REG 3 30 Integrated 2.5-V regulator output VSS 4, 23 4,32 Power supply ground XRST 5 1 Active-low output SRN 6 2 Current sense terminal Current sense positive terminal when charging relative to SRN; current sense negative SRP 7 3 terminal when discharging relative to SRN Sense voltage input terminal for most negative cell; balance current input for least positive VC5 8 4 cell. Sense voltage input terminal for least positive cell, balance current input for least positive cell, VC4 9 5 and return balance current for third most positive cell. Sense voltage input terminal for third most positive cell, balance current input for third most VC3 10 6 positive cell, and return balance current for second most positive cell. Sense voltage input terminal for second most positive cell, balance current input for second VC2 11 7 most positive cell, and return balance current for most positive cell. Sense voltage input terminal for most positive cell, balance current input for most positive cell, VC1 12 8 and battery stack measurement input BAT 13 10 Charge pump, charge N-CH FET gate drive CHG 14 11 Charge pump, charge N-CH FET gate drive DSG 16 13 Charge pump output, discharge N-CH FET gate drive PACK 17 14 PACK positive terminal and alternative power source VCC 19 16 Power supply voltage ZVCHG 20 17 Connect the precharge P-CH FET drive here GPOD 21 18 NCH FET open-drain output PMS 22 19 Determines CHG output state on POR LEDOUT 24 21 3.3-V output for LED display power supply TOUT 25 22 Provides thermistor bias current Digital input that provides the timing clock for the OC and SC delays and also acts as the WDI 26 23 watchdog clock. SCLK 28 25 Open-drain serial interface clock with internal 10-k Ω pullup to V REG SDATA 29 26 Open-drain bidirectional serial interface data with internal 10-k Ω pullup to V REG Open-drain output used to indicate status register changes. With internal 100-k Ω XALERT 30 27 pullup to VREG NC 15,18,27 9,12,15, 24,31 Not electrically connected to the IC 3 |
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