DDC’s BUS-61559 series of Advanced
Integrated Mux Hybrids with enhanced
RT Features (AIM-HY’er) comprise a
complete interface between a micro-
processor and a MIL-STD-1553B
Notice 2 bus, implementing Bus
Controller (BC), Remote Terminal (RX,
and Monitor Terminal (MT) modes.
Packaged in a single 78-pin DIP or
82-pin flat package the BUS-61559
series contains dual low-power trans-
ceivers and encoder/decoders, com-
plete BC/RT/MT protocol logic, memory
management and interrupt logic, 8K x 16
of shared static RAM, and a direct,
buffered interface to a host processor bus.
The BUS-61559 includes a number of
advanced features in support of
MIL-STD-1553B Notice 2 and STANAG
3838. Other salient features of the
BUS-61559 serve to provide the bene-
fits of reduced board space require-
ments enhanced software flexibility,
and reduced host processor overhead
The BUS-61559 contains internal
address latches and bidirectional data
buffers to provide a direct interface to
a host processor bus. Alternatively,
the buffers may be operated in a fully
transparent mode in order to interface
to up to 64K words of external shared
RAM and/or connect directly to a com-
ponent set supporting the 20 MHz
STANAG-3910 bus.
The memory management scheme
for RT mode prevails an option for
separation of broadcast data, in com-
pliance with 1553B Notice 2. A circu-
lar buffer option for RT message data
blocks offloads the host processor for
bulk data transfer applications.
Another feature besides those listed
to the right, is a transmitter inhibit con-
trol for the individual bus channels.
The BUS-61559 series hybrids oper-
ate over the full military temperature
range of -55 to +125”C and MIL-PRF-
38534 processing is available. The
hybrids are ideal for demanding mili-
tary and industrial microprocessor-to-
1553 applications
MIL-STD-1553B NOTICE 2
ADVANCED INTEGRATED MUX HYBRIDS
WITH ENHANCED RT FEATURES (AIM-HY’er)
FEATURES
• Complete Integrated 1553B
Notice 2 Interface Terminal
• Functlonal Superset of BUS-
61553 AlM-HYSeries
• Internal Address and Data
Buffers for Dlrect Interface to
Processor Bus
• RT Subaddress Circular Buffers
to Support Bulk Data Transfers
• Optlonal Separatlon of
RT Broadcast Data
• Internal Interrupt Status and
Time Tag Registers
• Internal ST Command
Illegalization
• MIL-PRF-38534 Processing
Available
8
(ILLEGALIZATION
ENABLE)
ILLENA
BUS-25679
7
5
4
1
2
3
LOW-POWER
TRANSCEIVER
A
TX_INH_A
8
BUS-25679
7
5
4
1
2
3
LOW-POWER
TRANSCEIVER
A
TX_INH_A
(RT ADDRESS)
RTAD 4-
∅, RTADP
(BROADCAST
ENABLE)
BRO_ENA
RTFAIL
(RTFAIL,
RTFLAG)
RTFLAG
(BROADCAST,
MESSAGE
TIMING, DATA
STROBE AND ERROR
INDICATORS)
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
ILLEGALLIZATION
LOGIC
DUAL
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
8K x 16
DUAL
PORT
RAM
MEMORY DATA
MEMORY ADDRESS
MEMORY
MANAGEMENT,
SHARED
RAM/
PROCESSOR
INTERFACE,
INTERRUPT
LOGIC
TAGCLK
SSFLAG
MEMENA-IN
MEMEN-OUT,MEMWR, MEMOE
INT
IOEN, READYD
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
(TIME TAG
CLOCK)
(SUBSYSTEM
FLAG)
(MEMORY
CONTROL)
(INTERRUPT
REQUEST)
(PROCESSOR
CONTROL)
ADDRESS
LATCHES/
BUFFERS*
ADDR_LAT
A15-A
∅
D15-D
∅
DATA
BUFFERS*
CLK IN (16MHz)
(PROCESSOR
DATA)
(PROCESSOR
ADDRESS)
(ADDRESS
LATCH
CONTROL)
BU-61559 BLOCK DIAGRAM
DESCRIPTION
© 1990, 1999 Data Device Corporation
BUS-61559 SERIES