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NCP4561 Datasheet(PDF) 9 Page - ON Semiconductor |
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NCP4561 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 16 page NCP4561 http://onsemi.com 9 Understanding the Load Transient Improvement The NCP4561 features a novel architecture which allows the user to easily implement the regulator in burst systems where the time between two current shots is kept very small. The quality of the transient response time is related to many parameters, among which the closed–loop bandwidth with the corresponding phase margin plays an important role. However, other characteristics also come into play like the series pass transistor saturation. When a current perturbation suddenly appears on the output, e.g. a load increase, the error amplifier reacts and actively biases the PNP transistor. During this reaction time, the LDO is in open–loop and the output impedance is rather high. As a result, the voltage brutally drops until the error amplifier effectively closes the loop and corrects the output error. When the load disappears, the opposite phenomenon takes place with a positive overshoot. The problem appears when this overshoot decays down to the LDO steady–state value. During this decreasing phase, the LDO stops the PNP bias and one can consider the LDO asleep. If by misfortune a current shot appears, the reaction time is incredibly lengthened and a strong undershoot takes place. This reaction is clearly not acceptable for line sensitive devices, such as VCOs or other Radio–Frequency parts. This problem is dramatically exacerbated when the output current drops to zero rather than a few mA. In this later case, the internal feedback network is the only discharge path, accordingly lengthening the output voltage decay period. The NCP4561 cures this problem by implementing a clever design where the LDO detects the presence of the overshoot and forces the system to go back to steady–state as soon as possible, ready for the next shot, which positively improves the response time and decreases the negative peak voltage. NCP4561 has a fast start–up phase Thanks to the lack of bypass capacitor the NCP4561 is able to supply its downstream circuitry as soon as the OFF to ON signal appears. In a standard LDO, the charging time of the external bypass capacitor hampers the response time. A simple solution consists in suppressing this bypass element but, unfortunately, the noise rises to an unacceptable level. NCP4561 offers the best of both worlds since it no longer includes a bypass capacitor and starts in less than 40 ms typically (Repetitive at 200 Hz). It also ensures a low–noise level of 40 mVRMS 100 Hz–100 kHz. The following picture details the typical NCP4561 startup phase. ON/OFF Pin Voltage 1 V/div Ch3 1.00 V Ch4 500 mV M 10.0 ms Ch3 1.82 V Figure 12. Start–Up Waveform (Conditions: Vin = 3.8 V, Iload = 10 mA, Cout = 1 mF) C4 High 2.78 V C4 Mean 2.426 V Tek Run: 5.00 MS/s Sample Vout 500 mV/div |
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