SPL31A
5.5. Timer/Counter
SPL31A contains two 16-bit timer/counters, TM0 and TM1
respectively. In the timer mode, TM0 and TM1 are reloadable
up-counters. When the timer overflows from $FFFF to $0000,
the carry signal will generate the INT signal if the corresponding
bit is enabled in INT ENABLE register ($0D).
The timer will
automatically reload the value assigned by the program and up
count continuously. If TM0 is specified as a counter, the user can
reset the counter by loading 0 into register $10 and $11 and
loading 0 into the counter by writing any data to $12. After the
counter is activated, the counter’s value can also be read from
above registers ($10 and $11) and the read instruction will not
affect the counter's value or reset it.
The clock source of the timer/counter are selected as the following:
Timer/Counter
Address
Clock Source
16-BIT Timer
$0010
$0011
$0012
R-oscillator Output, the CARRY of timer 1
TM0
16-BIT Counter
$0010
$0011
$0012
Clock source A: IOCD0, R-oscillator Output, VDD, 32768Hz.
Clock source B: IOCD1, VDD, T16Hz, 128Hz.
Note: T16Hz can be one of 4Hz, 8Hz, 16Hz and 32Hz by setting $0A (time-setting register)
TM1
16-BIT Timer
$0013
$0014
$0015
R-oscillator Output, 32768 Hz
Mode Select Register
$000B
Select TM0 & TM1 configuration
5.6. Speech and Melody
Since SPL31A can provide a large ROM size and wide CPU
operation speed, it is suitable for speech and melody synthesis.
For speech synthesis, this chip can provide INT for precise
sampling frequency. Users can record or synthesize the sound
and digitize the data into the ROM. The sound can be played
back in the sequence designed by the internal user's program.
Several algorithms are recommended for high fidelity and good
compression of sound: such as PCM and ADPCM.
For melody
synthesis, SPL31A provides dual tone mode. Once in the dual
tone mode, users only need to program the tone frequency of
each channel by writing to timer/counter TM0 and TM1, and set
the envelope of each channel. The hardware will toggle the tone
wave automatically without users’ care.
5.7. LCD Controller/Driver
SPL31A contains a LCD controller and driver for 220dots LCD
display. Users can set the LCD configuration (bias, duty, display
mode) by writing LCD control register ($18).
Once the LCD
configuration is initialized, the desired pattern can be displayed by
filling the LCD buffer with appropriate data. The LCD driver can
still operate during halt mode by keeping 32768 oscillator running.
Furthermore, programmer can turn off the LCD display through
LCD control register for power saving.
The LCD driver in
SPL31A is designed to fit most LCD's specifications. 1/2 or 1/3
bias are available from the LCD driver. Meanwhile, The display
duty can be programmed as 1/2, 1/3, 1/4 or 1/5 duty.
5.8. Voltage Doubler/Regulator
To get the best LCD quality, the LCD supply voltage should not
change with the system power. The SPL31A provides a robust
and adjustable (16-level) LCD supply voltage.
Users can get
desired VLCD to fit specific LCD panels by changing the output
reference voltage (program $16). The available VLCD voltage
range are summarized as the following table:
Bias
Min. VLCD ($16 = 00h)
Max. VLCD ($16 = 0Fh)
1/2 bias
2.0V
4.0V
1/3 bias
3.0V
6.0V
Note1: If the LCD display is uneven with a large panel load, connect a
resistor between the VDD1 pin and ground is suggested.
Note2: To make sure the chip work properly, the following equation must be
satisfied.
Min. (VLCD) > VDD, Otherwise, VDD will change the VLCD.
5.9. PWM Output
Internally, SPL31A has one pair of PWM outputs supporting two
sound channels. Each channel can be set to play speech or tone
individually. SPL31A uses Pulse Width Modulation that is able to
drive speaker or buzzer directly without any buffer or amplification
circuit.
5.10. Low Voltage Reset
The SPL31A provides a low voltage reset function. The system
will enter into LVRST state if and only if the power supply voltage
VDD is lower than 2.3V.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
6
AUG. 10, 2001
Version: 1.2