Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

f

ACLK

Ancillary / Control Data

Clock Frequency

A

CLK

V

CLK

MHz

DC

ACLK

Duty Cycle, Ancillary Clock

45

50

55

%

t

Ancillary / Control Clock

and Data Rise Time, Fall

Time

10%–90%

1.0

1.5

3.0

ns

t

S

Setup Time, AD

or IO

Edge

Control Data Input or

I/O Bus Input

IO

Timing Diagram

3.0

1.5

ns

t

H

Hold Time, Rising Edge

A

IO

N

3.0

1.5

ns

R

REF

Bias Supply Reference

Resistor

Tolerance 1%

4.75k

Ω

f

EXT CLK

External Clock Frequency

Ext Clk

−100

ppm

27.0

+100

ppm

MHz

f

XTAL

Crystal Frequency

Figure 6

XTALo, XTALi

DC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

V

IH

Input Voltage High Level

All LVCMOS

Inputs

2.0

V

DDIO

V

V

IL

Input Voltage Low Level

V

SSIO

0.8

I

IH

Input Current High Level

V

+85

+150

µA

I

IL

Input Current Low Level

V

−1

−20

V

OH

Output Voltage High Level

I

All LVCMOS

Outputs

2.4

2.7

V

DDIO

V

V

OL

Output Voltage Low Level

I

V

SSIO

V

SSIO

+0.3

V

SSIO

+0.5V

V

OHV

Minimum Dynamic V

OH

I

(Note 6)

V

DDIO

−0.5

V

OLP

Maximum Dynamic V

OL

I

(Note 6)

V

SSIO

+0.4

V

SDI

Serial Data Input Voltage

SDI, SDI

125

800

880

mV

P-P

I

SDI

Serial Data Input Current

µA

V

TH

Input Thereshold

Over VCM range

mV

I

BB

Bias Supply Output

Current

R

Ω 1%

−220

−188

µA

I

REF

Reference Output Current

R

Ω 1%

−290

−262

I

Power Supply Current,

3.3V Supply, Total

270M

V

38.0

45.0

mA

1,485M

47.0

50.0

I

Power Supply Current,

2.5V Supply, Total

270M

V

80

120

mA

1,485M

220

340

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