Philips Semiconductors

TDA8768A

12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Product data

Rev. 02 — 03 July 2002

11 of 32

9397 750 09656

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

[1]

D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested.

[2]

The circuit has two clock inputs: CLK and CLK. There are 5 modes of operation:

signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.

signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.

d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level

of 2.5 V, the sampling takes place at the falling edge of the clock signal.

When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to

decouple the CLK or CLK input to DGND via a 100 nF capacitor.

e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.

In that case CLK pin has to be connected to the ground.

[3]

see Figure 12.

[4]

The

−3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.

[5]

Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:

where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.

[6]

Signal-to-noise ratio (SNR) takes into account all harmonics above five and noise up to nyquist frequency; see Figure 8.

[7]

Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up

to half of the clock frequency (Nyquist frequency). Conversion to SINAD is given by SINAD = ENOB

× 6.02 + 1.76 dB; see Figure 5.

[8]

Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the

same amplitude and the total amplitude of both signals provides full-scale to the converter (

−6 dB below full scale for each input signal).

[9]

3-state output delay times; see Figure 4

enable HIGH

C

-

5.1

9.0

ns

enable LOW

C

-

7.0

11

ns

disable HIGH

C

-

9.7

14

ns

disable LOW

C

-

9.5

13

ns

Table 6:

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

THD

20 log

2nd

()

2

3rd

()

2

4th

()

2

5th

()

2

6th

()

2

++

+

+

F

2

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