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54F407SDMQB Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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54F407SDMQB Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 10 page  Unit LoadingFan Out 54F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL D0–D3 Data Inputs (Active LOW) 10067 20 mA b04 mA I0–I3 Instruction Word Inputs 10067 20 mA b04 mA CI Carry Input (Active LOW) 10067 20 mA b04 mA CO Carry Output (Active LOW) 20133 (067) 04 mA8 mA (4 mA) CP Clock Input (L-H Edge-Triggered) 10067 20 mA b04 mA EX Execute Input (Active LOW) 10067 20 mA b04 mA EOX Address Output Enable Input (Active LOW) 10067 20 mA b04 mA EO0 Data Output Enable Input (Active LOW) 10067 20 mA b04 mA X0–X3 Address Outputs 284 (100)267 (133) b57 mA (2 mA)16 mA (8 mA) O0–O3 Data Outputs (Active LOW) 284 (100)267 (133) b57 mA (2 mA)16 mA (8 mA) Functional Description The ’F407 contains a 4-bit slice of three Registers (R0–R2) a 4-bit Adder a TRI-STATE Address Output Buffer (X0–X3) and a separate Output Register with TRI-STATE buffers (O0–O3) allowing output of the register contents on the data bus (refer to the Block Diagram) The DAR performs sixteen instructions selected by I0–I3 as listed in the Func- tion Table The ’F407 operates on a single clock CP and EX are inputs to a 2-input active LOW AND gate For normal operation EX is brought LOW while CP is HIGH A microcycle starts as the clock goes HIGH Data inputs D0–D3 are applied to the Adder as one of the operands Three of the four instruction lines (I1–I2–I3) select which of the three registers if any is to be used as the other operand The LOW-to-HIGH CP transition writes the result from the Adder into a register (R0–R2) and into the output register provided EX is LOW If the I0 instruction input is HIGH the multiplexer routes the result from the Adder to the TRI-STATE Buffer controlling the address bus (X0–X3) independent of EX and CP The ’F407 is organized as a 4-bit register slice The active LOW CI and CO lines allow ripple-carry expansion over longer word lengths In a typical application the register utilization in the DAR may be as follows R0 is the Program Counter (PC) R1 is the Stack Pointer (SP) for memory resident stacks and R2 contains the operand address For an instruction Fetch PC can be gated on the X-Bus while it is being incremented (ie D-Bus e 1) If the fetched instruction calls for an effec- tive address for execution which is displaced from the PC the displacement can be added to the PC and loaded into R2 during the next microcycle Function Table Instruction Combinatorial Function Sequential Function Occurring I3 I2 I1 I0 Available on the X-Bus on the Next Rising CP Edge LLLL R0 R0 Plus D Plus CI x R0 and 0-Register LLL H R0 Plus D Plus CI L LHL R0 R0 Plus D Plus CI x R1 and 0-Register LL H H R0 Plus D Plus CI LHL L R0 R0 Plus D Plus CI x R2 and 0-Register LHLH R0 Plus D Plus CI LH HL R1 R1 Plus D Plus CI x R1 and 0-Register L HHH R1 Plus D Plus CI H LLL R2 D Plus CI x R2 and 0-Register H L L H D Plus CI HLHL R0 D Plus CI x R0 and 0-Register H L H H D Plus CI HH L L R2 R2 Plus D Plus CI x R2 and 0-Register H HLH R2 Plus D Plus CI HHH L R1 D Plus CI x R1 and 0-Register HHHH D Plus CI H e HIGH Voltage Level L e LOW Voltage Level 2 |
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