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SD60C32P Datasheet(PDF) 11 Page - AUK corp |
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SD60C32P Datasheet(HTML) 11 Page - AUK corp |
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11 / 13 page  KSI-W015-000 11 Timing Diagram (Continued) SD60C32/P SD60C52/P tQVWX ALE PSEN PORT0 PORT2 Figure 3. External Data Memory Write Cycle WR P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A15 FROM PCH tWHLH tLLWL tWLWH tWHQX tLLAX tAVLL tAVWL A0 - A7 FROM PCL INSTR IN DATA OUT A0 - A7 FROM RI OR DPL VCC - 0.5 0.45V 0.7VCC 0.2VSS -0.1 tCLCL tCLCX tCHCX tCLCH tCHCL Figure 4. External Clock Drive Figure 5. AC Testing Input/Output 0.2VCC +0.9 0.2VCC-0.1 VCC -0.5 0.45V NOTE : AC Inputs during testing are driven at VCC-0.5 for a logic '1' and 0.45V for a logic '0'. Timing measurements are made at V IH min for a logic '1' and V IL for a logic '0' Figure 6. Float Waveform NOTE : For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begings to float when a 100mV change from the loaded VOH /VOL level occurs. IOH/IOL 20mA TIMING REFERENCE POINTS VLOAD VLOAD - 0.1V VLOAD+ + 0.1V VOL + 0.1V VOH - 0.1V ≥ |
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