SPT
4
3/11/97
SPT7810
Figure 1A: Timing Diagram
tpwL
tpwH
Data Valid
N+1
N
N+1
N+2
Data Valid
N
CLK
Output
Data
CLK
td
Figure 1B: Single Event Clock
Data Valid
CLK
Output
Data
CLK
td
Table I - Timing Parameters
PARAMETERS
DESCRIPTION
MIN
TYP
MAX
UNITS
td
CLK to Data Valid Prop Delay
-
5
ns
tpwH
CLK High Pulse Width
20
-
300
ns
tpwL
CLK Low Pulse Width
20
-
-
ns
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
TEST LEVEL
I
II
III
IV
V
VI