SN54AHCT257, SN74AHCT257

QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS

WITH 3-STATE OUTPUTS

SCLS351E – MAY 1996 – REVISED OCTOBER 1998

2

POST OFFICE BOX 655303

2

1A

1

3

1B

5

2A

6

2B

11

3A

10

3B

14

4A

13

4B

EN

15

G1

1

MUX

1

1Y

4

2Y

7

3Y

9

4Y

12

OE

A/B

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.

logic diagram (positive logic)

4Y

3Y

2Y

1Y

A/B

OE

4B

4A

3B

3A

2B

2A

1B

1A

4

2

3

7

5

6

9

11

10

12

14

13

1

15

Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.