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M69KB096AA70CW8 Datasheet(PDF) 9 Page - STMicroelectronics |
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M69KB096AA70CW8 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 48 page  9/48 M69KB096AA be accessed. It also allows any pending refresh operations to be performed (see Figure 22., Continuous Burst Read Showing an Output Delay for End-of-Row Condition (BCR8=0,1)). The processor can access other devices without being submitted to the initial burst latency by sus- pending the burst operation. Burst operations can be suspended by halting the Clock signal, holding it High or Low. If another device needs to use the data bus while Burst operations are suspended, the Output Enable signal, G, should be driven High, VIH, to disable data outputs; otherwise, G can remain Low, VIL. The WAIT output will remain asserted to prevent any other devices from using the processor WAIT line. Burst operations can be resumed by taking G Low, VIL, and then restarting the Clock as soon as valid data are available on the bus (see Figure 21., Synchronous Burst Read Suspend and Re- sume Waveforms). Mixed Mode When the BCR register is configured for synchro- nous operation, the device can support a combina- tion of Synchronous Burst Read and Asynchronous Random Write operations. The Asynchronous Random Write operation re- quires that the Clock signal remains Low, VIL, dur- ing the entire sequence. The L signal can either be used to latch the target address or remain Low, VIL, during the entire Write operation. E must re- turn Low, VIL, during Asynchronous and Burst op- erations. Note that the time, necessary to assure adequate refresh, is the same value as that for Asynchronous Read and Write mode. Mixed-mode operation greatly simplifies the inter- facing with traditional burst-mode Flash Memory Controllers. Low-Power Modes Standby Mode. During Standby, the device cur- rent consumption is reduced to the level neces- sary to perform the memory array refresh operation. Standby operation occurs when E is High, VIH, and no transaction is in progress. The device will enter Standby mode when a Read or Write operation is completed, or when the ad- dress and control inputs remain stable for an ex- tended period of time. This “active” Standby mode will continue until address or control inputs change. Temperature Compensated Refresh. The Temperature Compensated Refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. The leakage current of DRAM capacitive storage elements increases with the temperature. PSRAM devices, based on a DRAM architecture, conse- quently require increasingly frequent refresh oper- ations to maintain data integrity as the temperature increases. At lower temperatures, the refresh rate can be decreased to minimize the standby current. The TCR mechanism allows adequate refresh rates to be set at four different temperature thresh- olds. These are defined by setting the RCR5 and RCR6 bits of the Refresh Configuration Register, RCR. To minimize the self refresh current con- sumption, the selected setting must be higher than the operating temperature of the PSRAM device. As an example, if the operating temperature is +50°C, the +70°C setting must be selected; the +15°C and +45°C settings would result in inade- quate refreshing and could cause data corruption. See Table 9. for the definition of the Refresh Con- figuration Register bits. Partial Array Refresh. The Partial Array Refresh (PAR) performs a limited refresh of part of the PSRAM array. This mechanism enables the de- vice to reduce the standby current by refreshing only the part of the memory array that contains es- sential data. Different refresh options can be de- fined by setting the RCR0 to RCR2 bits of the RCR Register: ■ Full array ■ One half of the array ■ One quarter of the array ■ One eighth of the array ■ None of the array. These memory areas can be located either at the top or bottom of the memory array. The WAIT signal is used for arbitration when a read/write operation is launched while an on-chip refresh is in progress. If locations are addressed while they are undergoing refresh, the WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see Figure 6. and Fig- ure 7., Collision between Refresh and Read or Write Operations). When the refresh operation is completed, the Read or Write operation will be al- lowed to continue normally. |
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