Rev. 1.2 - 3/31/98
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PRELIMINARY
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PDM31564
Description
The PDM31564 is a high-performance CMOS static
RAM organized as 262,144 x 16 bits. The PDM31564
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31564 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31564 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP package for high-density
surface assembly and is suitable for use in high-
speed applications requiring high-speed storage.
PDM31564
256K x 16 CMOS
3.3V Static RAM
A7-A0
Memory
Cell
Array
256 x 128 x 32
Control
Logic
Sense Amp
Column
Decoder
Column
Address
Buffer
Clock
Generator
A15-A8
CE
LB
UB
OE
WE
Data
Input/
Output
Buffer
Vcc
Vss
I/O15-I/O0
Features
n High-speed access times
- Com’l: 8, 10, 12, 15, and 20 ns
- Ind: 12, 15, and 20 ns
n Low power operation (typical)
- PDM31564SA
Active: 300 mW
Standby: 25mW
n High-density 256K x 16 architecture
n 3.3V (±0.3V) power supply
n Fully static operation
n TTL-compatible inputs and outputs
n Output buffer controls: OE
n Data byte controls: LB, UB
n Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
512 x 256 x 32
A8 - A0
A17 - A9
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