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P521-39DC Datasheet(PDF) 4 Page - PhaseLink Corporation |
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P521-39DC Datasheet(HTML) 4 Page - PhaseLink Corporation |
4 / 6 page Preliminary P521-39 Low Phase Noise LVDS VCXO (65MHz to 130MHz) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 3/02/04 Page 4 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (Loaded Outputs) IDD at 3.3V @ 77.76MHz 40 mA Oscillator off 10 Output valid after OE enabled Oscillator on 1 ms Operating Voltage VDD 2.25 3.63 V Output Clock Duty Cycle @ 1.25V (LVDS) 45 50 55 % Short Circuit Current ±50 mA 5. Jitter specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS at 77.76MHz 2.5 Period jitter peak-to-peak at 77.76MHz At 77.76MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles 18.5 20 ps Accumulated jitter RMS at 77.76MHz 2.5 Accumulated jitter peak-to-peak at 77.76MHz At 77.76MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. 24 27 ps Random Jitter “RJ” measured on Wavecrest SIA 3000 2.5 ps Integrated jitter RMS at 77.76MHz Integrated 12 kHz to 20 MHz 0.5 0.7 ps Measured on Wavecrest SIA 3000 6. Phase noise specifications PARAMETERS FREQUENCY 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz UNITS Phase Noise relative to carrier 77.76MHz -75 -100 -125 -140 -145 -150 dBc/Hz Note: Phase Noise measured at VCON = 0V |
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