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PLL602-41XDC Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL602-41XDC Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 4 page Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 2 PIN DESCRIPTIONS Name Number Type Description CLK 1 O Output clock pin. VDD 2 P +3.3V VDD power supply pin. OE 3 I Output enable input pin. Disables (tri-state) output when low. Internal pull- up enables output by default if pin is not connected to low. XIN 4 I Crystal input pin. XOUT 5 I Crystal output pin. N/C 6 - Not connected. GND 7, 8 P Ground pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage Range VCC -0.5 7 V Input Voltage Range VI -0.5 VCC +0.5 V Output Voltage Range VO -0.5 VCC +0.5 V Soldering Temperature 260 °C Storage Temperature TS -65 150 °C Ambient Operating Temperature 0 70 °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con- ditions above the operational limits noted in this specification is not implied. 2. AC Specification PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Input Frequency 12 24 MHz Output Frequency 48 96 MHz Output Rise Time 0.8V to 2.0V with no load 1.5 ns Output Fall Time 2.0V to 0.8V with no load 1.5 ns Duty Cycle At VDD/2 45 50 55 % |
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