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PLL602-89DSC-R Datasheet(PDF) 3 Page - PhaseLink Corporation |
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PLL602-89DSC-R Datasheet(HTML) 3 Page - PhaseLink Corporation |
3 / 5 page PLL602-89D 12-27 MHz XO IC with 2 Pairs of LVDS Outputs 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Fout = 12 MHz 15 20 Supply Current, Dy- namic (with Loaded Outputs) IDD LVDS outputs loaded with 100Ω Fout = 25 MHz 20 25 mA Operating Voltage VDD 2.25 3.63 V Short Circuit Current ±50 mA 4. AC Electrical Specifications 5. Jitter Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Input Crystal Frequency 12 27 MHz 0.8V ~ 2.0V with 10 pF load 1.5 Output Clock Rise Time 0.3V ~ 3.0V with 15 pF load 2 5 2.0V ~ 0.8V with 10 pF load 1.5 Output Clock Fall Time 3.0V ~ 0.3V with 15pF load 2 5 ns Measured @ 1.25 V (LVDS) 45 50 55 Output Clock Duty Cycle Measured @ VDD/2 (CMOS) 45 50 55 % PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS Period jitter RMS With capacitive decoupling between VDD and GND. 25MHz 2.5 4 ps Peak to Peak jitter With capacitive decoupling between VDD and GND. Over 10,000 cycles. 25MHz 18 30 ps |
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