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SCP600-27MSC Datasheet(PDF) 1 Page - PhaseLink Corporation |
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SCP600-27MSC Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 4 page Preliminary PLL600-27M Dual XO with 4 CMOS Outputs 10MHz to 52MHz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 1 FEATURES • Generates 4 CMOS outputs from 2 crystal inputs • XIN1- Accepts a 10 to 52MHz crystal input and generates 1 CMOS output at the same frequency. • XIN2- Accepts a 10 to 52MHz crystal input and generates 3 CMOS outputs at the same frequency. • Low phase noise (-130 dBc @ 10kHz offset). • Low jitter (RMS): 2.5ps period jitter. • 12mA drive capability at TTL output. • 1.62V to 3.63V DC operation. • Available in 14 pin 150mil SOIC. DESCRIPTION The PLL600-27M is part of PhaseLink ’s low cost family of XO IC’s, designed to replace multiple XO solutions saving the cost and board space of clock distribution buffers. In addition, this product family provides among the lowest current on the market for the 10MHz to 52MHz range. They accept input crystals from 10MHz to 52MHz (fundamental resonant mode) and provide low phase noise (<- 130dBc at 10kHz offset at 30MHz), and very low jitter (2.5 ps RMS period jitter) outputs. PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 XOUT1 N/C VDD CLK1 GND CLK2C XIN2 XIN1 GND GND CLK2A VDD CLK2B XOUT2 BLOCK DIAGRAM CLK2A CLK2B CLK2C CLK1 XIN1 XOUT1 XIN2 XOUT2 XTAL OSC XTAL OSC |
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Similar Description - SCP600-27MSC |
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