Preliminary

PLL702-03

Low EMI Peripheral Clock Generator for Notebook PCs

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 10/06/02 Page 2

BLOCK DIAGRAM

Note: In order to use VDD25M as power source for 8MHz (pin 13), 24.576MHz (pin 7), and 12MHz (pin 12), it is necessary to select this feature

through the VDD_SEL input (see Power Selection Table on p.1).

Note 2: Only 27MHz output is modulated for low EMI via Spread Spectrum.

SSC(0:1)

PLL2

25MHz

27_14.318MHz

VDDB2

VDD25M

XTAL

OSC

XIN

XOUT

PLL

SST

24.576MHz

(pin7)

VDDB1

12MHz

VDDB2

8MHz

VDDB2

VDD25M

24.576MHz

(pin6)

VDDB1

VDD25M

VDD25M