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PLL701-31SI Datasheet(PDF) 4 Page - PhaseLink Corporation |
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PLL701-31SI Datasheet(HTML) 4 Page - PhaseLink Corporation |
4 / 5 page PLL701-31 Low EMI Spread Spectrum Multiplier Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4 2. DC/AC Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Voltage VDD 2.7 3.0 3.3 V Input High Voltage VIH 0.7* VDD V Input Low Voltage VIL 0.3* VDD V Input High Current IIH 100 µA Input Low Current IIL 100 µA Output High Voltage VOH IOH=5mA, VDD =3.3V 2.4 Output Low Voltage VOL IOL=6mA, VDD =3.3V 0.4 FXIN When using a crystal 10 30 MHz Input Frequency FIN When using reference clock 10 30 MHz Maximum interruption of FIN When using reference clock 100 µs Load Capacitance CL Between Pin XIN and XOUT* 18 pF Pull-up Resistor Rup PIN 2 120 k Ω Pull-up Resistor Rup PIN 3, 4, 7 30 k Ω Short Circuit Current Isc 50 mA 3.3V Dynamic Supply Current ICC No Load 18 mA *Note: Pin XIN and XOUT each has a 36pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 18pF. If driving XIN with a reference clock signal, the load capacitance will be 36pF (typical). 3. Timing Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Rise Time Tr Measured at 0.8V ~ 2.0V @ 3.3V 0.8 0.95 1.1 ns Fall Time Tf Measured at 2.0V ~ 0.8V @ 3.3V 0.78 0.85 0.9 ns Output Duty Cycle DT 45 50 55 % Cycle to Cycle Jitter Tcyc-cyc FOUT=48MHz @ 3.3V 100 ps Cycle to Cycle Jitter Tcyc-cyc FOUT=72MHz @ 3.3V 100 ps |
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