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MAX3881ECB Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX3881ECB Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 11 page +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery _______________________________________________________________________________________ 5 NAME FUNCTION 1, 15, 16, 17, 25, 33, 41, 49, 57, 62, 64 GND Ground PIN Pin Description 2 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 3 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 4, 7, 10, 13, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60 VCC +3.3V Supply Voltage 5 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 6 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 8 SDI+ Positive Serial Data Input. 2.488Gbps data stream. 9 SDI- Negative Serial Data Input. 2.488Gbps data stream. 11 SLBI+ Positive System Loopback Input. 2.488Gbps data stream. 12 SLBI- Negative System Loopback Input. 2.488Gbps data stream. 14 SIS Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input (SLBI). 18 PCLK+ Positive Parallel Clock PECL Output 19 PCLK- Negative Parallel Clock PECL Output 21, 23, 27, 29, 31, 35, 37, 39, 43, 45, 47, 51, 53, 55, 59, 61 PD0 to PD15 Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK signal (Figure 2). 63 LOL Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10k Ω pullup resistor). The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881. EP Exposed Pad Ground. This must be soldered to a circuit board for proper electrical and thermal performance (see Package Information). |
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