TMS416400A, TMS417400A

4194304 BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997

7

POST OFFICE BOX 1443

test mode (continued)

Test Mode Cycle

Entry Cycle

Exit Cycle

Normal

Mode

RAS

CAS

W

NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.

Figure 1. Test-Mode Cycle