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ICS525RI07LF Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS525RI07LF Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 9 page LVCMOS User Configurable Clock MDS 525-07/08 A 3 Revision 101105 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS525-07/08 PRELIMINARY INFORMATION Pin Assignment (ICS525-08) Pin Descriptions (ICS525-08) 18 7 17 8 16 9 15 X1/ICLK 10 X2 11 GND 12 CLK 13 V0 14 V1 GND PD V8 V2 V7 V5 V3 V6 22 21 20 19 V4 REF 5 6 S2 VDD VDD 24 23 R0 3 4 S0 S1 R1 26 25 R2 1 2 R5 S3 R3 28 27 R4 Pin Number Pin Name Pin Type Pin Description 1, 24-28 R5, R0-R4 I(PU) Reference divider word input pins. 2, 3, 4, 5 S0, S1, S2, S3 I(PU) Select pins for output divider. See table on page 4. 6, 23 VDD Power Connect to VDD. 7 X1/ICLK X1 Crystal connection. Connect to a parallel resonant fundamental crystal or input clock. 8 X2 X2 Crystal connection. Connect to a crystal or leave unconnected for clock. 9, 20 GND Power Connect to ground. 10 - 18 V0 - V8 I(PU) VCO divider word input pins. 19 PD Input Power-down. Active low. Turns off entire chip when low. Clock outputs stop low. 21 CLK Output PLL output clock. 22 REF Output Reference output. Buffered crystal oscillator (or clock) output. |
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