3

Rev. 00G

01/15/07

IS93C46D

Write All (WRALL)

The write all (WRALL) instruction programs all registers with

the data pattern specified in the instruction. As with the

WRITE instruction, the falling edge of CS must occur to

initiate the self-timed programming cycle. If CS is then

pin indicates the READY/

BUSY status of the chip (see

Figure 6). Vcc is required to be above 4.5V for WRALL to

function properly.

Write Disable (WDS)

The write disable (WDS) instruction disables all programming

capabilities. This protects the entire device against acci-

dental modification of data until a WEN instruction is

executed. (When Vcc is applied, this part powers up in the

write disabled state.) To protect data, a WDS instruction

should be executed upon completion of each programming

operation.

Erase Register (ERASE)

After the erase instruction is entered, CS must be brought

LOW. The falling edge of CS initiates the self-timed internal

programming cycle. Bringing CS HIGH after a minimum of

BUSY status of the

chip: a logical “0” indicates programming is still in progress;

a logical “1” indicates the erase cycle is complete and the

part is ready for another instruction (see Figure 8).

Erase All (ERAL)

Full chip erase is provided for ease of programming. Erasing

the entire chip involves setting all bits in the entire memory

array to a logical “1” (see Figure 9). Vcc is required to be

above 4.5V for ERAL to function properly.

Write Enable (WEN)

The write enable (WEN) instruction must be executed

before any device programming (WRITE, WRALL, ERASE,

and ERAL) can be done. When Vcc is applied, this device

powers up in the write disabled state. The device then

remains in a write disabled state until a WEN instruction is

executed. Thereafter, the device remains enabled until a

WDS instruction is executed or until Vcc is removed. (See

Figure 4.) (Note: Chip select must remain LOW until Vcc

reaches its operational value.)

Write (WRITE)

The WRITE instruction includes 8 or 16 bits of data to be

written into the specified register. After the last data bit has

CS must be brought LOW. If the device is write-enabled,

then the falling edge of CS initiates the self-timed program-

ming cycle (see WEN).

If CS is brought HIGH, after a minimum wait of 200 ns (5V

the READY/

BUSY status of the chip. Logical “0” means

programming is still in progress; logical “1” means the

selected register has been written, and the part is ready for

another instruction (see Figure 5). The READY/

BUSY

status will not be available if: a) The CS input goes HIGH

Simultaneously CS is HIGH, Din is HIGH, and SK goes

HIGH, which clears the status flag.

INSTRUCTION SET - IS93C46D (1Kb)

8-bit Organization

16-bit Organization

(ORG = GND)

(ORG = Vcc)

Start Bit

OP Code

Input Data

READ

1

10

1

00

11xxxxx

—

11xxxx

—

WRITE

1

01

1

00

01xxxxx

01xxxx

1

00

00xxxxx

—

00xxxx

—

ERASE

1

11

1

00

10xxxxx

—

10xxxx

—

Notes:

1. x = Don't care bit.

2. If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored,

and WRITE, WRALL, ERASE, ERAL are also ignored, and READ, WEN, WDS are accepted.