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ICS557G-05ALF Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS557G-05ALF Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 12 page Quad Differential PCI-Express Clock Source MDS 557-05A E 5 Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Output Structures General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-05A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. R R 475 6*IREF =2.3 mA IREF See Output Termination Sections - Pages 3 ~ 5 Ω |
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