ICS558G-02 datasheet(1/5 Pages) ICST

Part #	ICS558G-02

Description	LVHSTL TO CMOS CLOCK DIVIDER

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ICS558-02

MDS 558-02 D

1

Revision 020504

Integrat ed Circuit Systems ● 525 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m

LVHSTL TO CMOS CLOCK DIVIDER

Description

The ICS558-02 accepts a high-speed LVHSTL input

and provides four CMOS low skew outputs from a

selectable internal divider (divide by 3, divide by 4). The

four outputs are split into two banks of two outputs.

Each bank has a separate output enable to tri-state the

output buffers.

The ICS558-02 is a member of the ICS Clock BlocksTM

family of clock generation, synchronization, and

distribution devices.

Features

• 16-pin TSSOP package

• LVHSTL inputs

• Accepts up to 250 MHz input frequency

• Four low skew (<250 ps) outputs

• Selectable internal divider of 3 or 4

• Operating voltage of 3.3 V

Block Diagram

OE1

CLK1

CLK2

CLK3

CLK4

HCLK

Output Divide

/3 or /4

HCLK

SEL

GND

VDD

OE0

4

3

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