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ICS83056AI01 Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS83056AI01 Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 12 page Integrated Circuit Systems, Inc. 83056AGI-01 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 7, 2005 7 ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER PRELIMINARY ADDITIVE PHASE JITTER Additive Phase Jitter (Random) at 155.52MHz (12KHz - 20MHz) = 0.07ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in As with most timing specifications, phase noise measure- ments have issues. The primary issue relates to the limita- tions of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated the 1Hz band to the power in the fundamental. When the re- quired offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the funda- mental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) |
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