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ICS8523AI03L Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS8523AI03L
Description  LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS8523AI03L Datasheet(HTML) 1 Page - Integrated Circuit Systems

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8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8523I-03
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS8523I-03
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
nc
nc
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
nQ3
GENERAL DESCRIPTION
The ICS8523I-03 is a low skew, high perfor-
mance 1-to-4 Differential-to-LVHSTL fanout buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8523I-03 has two selectable clock inputs.
The input pairs can accept most standard differential input
levels. The clock enable is inter nally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523I-03 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
• 4 differential LVHSTL compatible outputs
• Selectable differential CLK0, nCLK0 and CLK1, nCLK1
clock inputs
• Clock input pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.2ns (typical)
• V
OH = 1V (maximum)
• 3.3V core, 1.8V output operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
HiPerClockS™
ICS
CLK0
nCLK0
CLK1
nCLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE


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