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ICS83841BH Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS83841BH Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 8 page 83841BH www.icst.com/products/hiperclocks.html REV. A JANUARY 20, 2006 1 Integrated Circuit Systems, Inc. ICS83841 20 BIT, DDR SDRAM 2:1 MUX GENERAL DESCRIPTION The ICS83841 is a 20 Bit, DDR SDRAM 2:1 MUX and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The device has 20 host lines and each host line can be passed to 2 data ports. The host/data ports are compatible with single-ended SSTL-2 and the device op- erates from a 2.5V supply. Guaranteed low output skew makes the ICS83841 ideal for demanding applications which require well defined performance and repeatability. LOGIC DIAGRAM FEATURES • Forty low skew single-ended DIMM ports • One SSTL-2 compatible select input • Maximum Switching Speed: 3ns • Output skew: 180ps (maximum) • r on = 20 Ω (typical) • Full 2.5V supply modes • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages HiPerClockS™ ICS SIMPLIFIED SCHEMATIC DHx S DAx or DBx RPD SW DH0 DA0 DB0 DH19 Sw Sw DA19 DB19 Sw Sw S ron ron ICS83841 72-Ball TFBGA 6mm x 6mm x 1.2mm package body H Package Top View PIN ASSIGNMENT B D 7 1 A D 7 1 B D 6 1 B D 5 1 A D 5 1 B D 4 1 A D 4 1 A D 3 1 B D 2 1 A D 2 1 A D 8 1 H D 7 1 H D 6 1 A D 6 1 H D 5 1 H D 4 1 B D 3 1 H D 3 1 H D 2 1 B D 1 1 B D 8 1 H D 8 1 D N GD N GH D 1 1 A D 1 1 A D 9 1 D N GD N GB D 0 1 B D 9 1 H D 9 1 SV D D H D 0 1 A D 0 1 A D 0 H D 0 V D D V D D H D 9 B D 9 B D 0 D N GD N GA D 9 A D 1 H D 1 D N GD N GH D 8 B D 8 B D 1 H D 2 H D 3 B D 3 H D 4 H D 5 A D 6 H D 6 H D 7 A D 8 A D 2 B D 2 A D 3 A D 4 B D 4 A D 5 B D 5 B D 6 A D 7 B D 7 1 2 34 5 6 789 10 A B C D E F G H J K |
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