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ICS83940DYI-01T Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS83940DYI-01T Datasheet(HTML) 9 Page - Integrated Circuit Systems |
9 / 13 page 83940DYI-01 www.icst.com/products/hiperclocks.html REV. A MARCH 1, 2004 9 Integrated Circuit Systems, Inc. ICS83940I-01 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER PRELIMINARY APPLICATION INFORMATION Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R2 1K V_REF C1 0.1u R1 1K Single Ended Clock Input PCLK nPCLK |
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