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PE84244-01 Datasheet(PDF) 5 Page - Peregrine Semiconductor Corp. |
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PE84244-01 Datasheet(HTML) 5 Page - Peregrine Semiconductor Corp. |
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5 / 6 page  PE84244 Preliminary Specification PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 5 of 7 VDD CNTL GND RFC RF1 GND GND RF2 100 pF Optional 100 pF Optional J2-7 J2-3 J1 J3 J4 J6 J8 Evaluation Kit Information Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE84244 SPDT switch. The RF common port is connected through a 50Ω transmission line to the top left SMA connector, J1. Port 1 and Port 2 are connected through 50Ω transmission lines to the top two SMA connectors on the right side of the board, J3 and J4. A through transmission line connects SMA connectors J6 and J8. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.030”, trace gaps of 0.007”, dielectric thickness of 0.028”, metal thickness of 0.0014” and εr of 4.4. J2 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device CNTL input. The fourth pin to the right (J2-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CNTL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. Figure 12. Evaluation Board Layouts Figure 13. Evaluation Board Schematic |
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