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ICS671M-06ILFT Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS671M-06ILFT Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 6 page 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER MDS 671-06 D 2 Revision 050405 Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com ICS671-06 Pin Assignment Output Clock Mode Select Table Note 1. Outputs are in high impedance state. Note 2. Buffer mode only; not zero delay between input and output. Pin Descriptions 12 1 11 2 10 CL K IN FB IN 3 9 CL K A 1 4 CL K A 2 C L KA4 5 VD D 6 C L KA3 7 GN D 8 CL K B 1 VD D GN D C L KB4 CL K B 2 C L KB3 S2 S1 16 15 14 13 16 p in na rro w (1 50 m il) S O IC a nd 16 pin (1 73 m il ) T S S O P S2 S1 CLKA1:A4 CLKB1:B4 A & B Source PLL Status 0 0 Tri-state (note 1) Tri-state (note 1) PLL OFF 0 1 Running Tri-state (note 1) PLL ON 1 0 Running Running CLKIN (note 2) OFF 1 1 Running Running PLL ON Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input Clock input. 2 - 3, 14 - 15 CLKA1:A4 Output Clock outputs A1:A4. See table above. 4 VDD Power Power supply. Connect to 3.3 V. 5 GND Power Connect to ground. 6 - 7, 10 - 11 CLKB1:B4 Output Clock outputs B1:B4. See table above. 8 S2 Input Select input 2. See table above. Internal pull-up. 9 S1 Input Select input 1. See table above. Internal pull-up. 12 GND Power Connect to ground. 13 VDD Power Power supply. Connect to 3.3 V. 16 FBIN Input Feedback input. Connect to any output under normal operation. |
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