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ICS7152M-02LF Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS7152M-02LF Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 9 page Spread Spectrum Clock Generator MDS 7152 E 3 Revision 012306 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS7152 External Components The ICS7152 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between GND and VDD on pin 6, as close to this pin as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor Series termination should be used on the clock output. To series terminate a 50 Ω trace (a commonly used trace impedance) place a 27 Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 25 Ω. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS7152. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Crystal Information The crystal used should be a fundamental mode, parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used. Spread Spectrum Profile The ICS7152 low EMI clock generator uses a triangular frequency modulation profile for optimal down stream tracking of zero delay buffers and other PLL devices. The frequency modulation amplitude is constant with variations of the input frequency. Time Modulation Rate |
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