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ICS853013AMLF Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS853013AMLF Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 17 page 853013AM www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 8 Integrated Circuit Systems, Inc. ICS853013 LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO- 2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V CC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V CC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R2 1K V_REF C1 0.1u R1 1K Single Ended Clock Input PCLK nPCLK INPUTS: PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from PCLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. |
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