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MAX3874 Datasheet(PDF) 2 Page - Maxim Integrated Products

Part # MAX3874
Description  MAX3872/MAX3874 Evaluation Kits
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX3874 Datasheet(HTML) 2 Page - Maxim Integrated Products

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MAX3872/MAX3874 Evaluation Kits
2 ________________________________________________________________________________________
_______________ Detailed Description
The MAX3872/MAX3874 EV Kit is a fully assembled
and factory tested demonstration board that enables
testing of all MAX3872 and MAX3874 functions.
Test Equipment Required
Test Equipment Required
Test Equipment Required
Test Equipment Required
+3.3V power supply with 200mA current capability
Signal-source, 2.7Gbps minimum capability
Jitter analyzer capable of 2.7Gbps performance
Oscilloscope with at least 3GHz performance
Test Equipment Interface
Test Equipment Interface
Test Equipment Interface
Test Equipment Interface
The serial inputs (SDI±, SLBI±) and serial outputs
(SDO±,
SCLKO±)
have
on-board
AC-coupling
capacitors to allow direct connection to 50
Ω test
equipment. The EV kit also has pads on the serial data
and clock outputs (SDO±, SCLKO±) to allow on-board
termination
for
coupling
to
high-impedance
oscilloscopes.
Quick Start (MAX3872 & MAX3874)
Quick Start (MAX3872 & MAX3874)
Quick Start (MAX3872 & MAX3874)
Quick Start (MAX3872 & MAX3874)
This procedure will set up the evaluation board for
2.48832Gbps normal operation mode, with input
threshold adjust disabled.
1) Place a shunt across pins 2 (SIS) and 3 (GND) of
J13.
2) Place a shunt across pins 1 (VCC) and 2 (LREF)
of J14.
3) Place a shunt across pins 2 and 3 of J15.
4) Place a shunt across pins 2 (RS1) and 3 (GND) of
J17.
5) Place a shunt across pins 2 (RS2) and 3 (GND) of
J18.
6) Place a shunt across pins 2 (RATESET) and 3
(GND) of J19.
7) Place a shunt across pins 1 (VCC) and 2 (VCTRL)
of J9.
8) Remove the shunt from J10.
9) Place a shunt across pins 2 (FREFSET) and 3
(GND) of J12.
10) Connect a 2.48832Gbps PRBS NRZ signal to the
serial data inputs (SDI±) with 50
Ω cables. Leave
the SLBI
± inputs unconnected.
11) Connect the serial data and clock outputs (SDO±,
SCLKO±) to a 50
Ω high-speed oscilloscope.
Terminate any unused outputs with 50
Ω to GND.
12) Connect +3.3V to J20 (VCC) and ground to J21
(GND).
Jitter analysis and product performance can also be
observed by appropriately interfacing the EV kit with a
bit-error-rate tester (BERT) and a jitter analyzer.
Operational Modes
Operational Modes
Operational Modes
Operational Modes
The
MAX3872/MAX3874
has
three
modes
of
operation: normal, system loopback, and clock
holdover.
The
three
operational
modes
are
programmed by connecting the appropriate pins of
JU13 (SIS) and JU14 (LREF). See Table 1. Normal
operation mode requires a serial data stream at the
SDI
± inputs, system loopback mode requires a serial
data stream at the SLBI
± inputs, and clock holdover
mode requires a reference clock signal at the SLBI
±
inputs.
Normal and System
Normal and System
Normal and System
Normal and System Loopback Settings
Loopback Settings
Loopback Settings
Loopback Settings
Three jumpers (RS1, RS2, RATESET) are available for
setting the SDI
± or SLBI± inputs to receive the
appropriate data rate (Table 2). The FREFSET pin can
be set high or low while in normal or system loopback
mode.
Clock Frequencies in Holdover Mode
Clock Frequencies in Holdover Mode
Clock Frequencies in Holdover Mode
Clock Frequencies in Holdover Mode
Set the incoming reference clock frequency and
outgoing serial clock frequency by setting RS1, RS2,
RATESET, and FREFSET appropriately. See Table 3.
Auto Switch to Clock Holdover Mode
Auto Switch to Clock Holdover Mode
Auto Switch to Clock Holdover Mode
Auto Switch to Clock Holdover Mode
To switch from normal mode to clock holdover mode
automatically when there are no data transitions
applied to the SDI
± inputs connect LOL directly to
LREF by placing a shunt across pins 1 and 2 of J15.
Vertical Threshold Adjustment
Vertical Threshold Adjustment
Vertical Threshold Adjustment
Vertical Threshold Adjustment
To compensate for optical noise presented on the data
logic high caused by EDFAs in a WDM transmission
system, an external analog control input is provided for
adjusting the data decision threshold to an optimum
level.
To enable data decision threshold adjustment, place a
shunt across pins 2 and 3 of J9 and shunt pins 1 and 2
of J10. Set the decision threshold by adjusting the
potentiometer R8. The center point for the decision
threshold is 1.2V at the VCTRL pin.
Jumpers, Controls, Test Points
Jumpers, Controls, Test Points
Jumpers, Controls, Test Points
Jumpers, Controls, Test Points
Table 4 summarises the functions of all jumpers,
controls, and test points of the MAX3872/MAX3874 EV
Kit.


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