PE9704

Advance Information

Copyright

File No. 70/0083~00B

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1 44 43 42 41 40

35

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36

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18 19 20 21 22 23 24 25 26 27 28

R

4

R

5

M

0

M

1

V

DD

V

DD

M

2

M

3

S_WR, M

4

DATA, M

5

GND

GND

N/C

V

DD

D

OUT

V

DD

N/C

GND

PD_D

PD_U

V

DD

C

EXT

Figure 2. Pin Configuration

Table 1. Pin Descriptions

Pin No.

Pin Name

Interface Mode

Type

Description

1

Both

(Note 1)

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing

recommended.

2

Direct

Input

R Counter bit0

3

Direct

Input

R Counter bit1

4

Direct

Input

R Counter bit2

5

Direct

Input

R Counter bit3

6

GND

Both

(Note 1)

Ground

7

Direct

Input

R Counter bit4

8

Direct

Input

R Counter bit5 (MSB)

9

Direct

Input

M Counter bit0

10

Direct

Input

M Counter bit1

11

Both

(Note 1)

Same as pin 1

12

Both

(Note 1)

Same as pin 1

13

Direct

Input

M Counter bit2

14

Direct

Input

M Counter bit3

S_WR

Serial

Input

Frequency register load enable input. Buffered data is transferred to the frequency

register on S_WR rising edge.

15

Direct

Input

M Counter bit4

16

DATA

Serial

Input

Binary serial data input. Data is entered LSB first, and is clocked serially into the 20-

bit frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR

“high”) on the rising edge of CLOCK.