ELECTRONICS

KM62V256C, KM62U256C Family

CMOS SRAM

Revision 04

April 1996

- 1 -

FEATURE SUMMARY

GENERAL DESCRIPTION

The KM62V256C and KM62U256C family are fabricated

by SAMSUNG's advanced CMOS process technology. The

family can support various operating temperature ranges

and has various package types for user flexibility of system

design. The family also support low data retention voltage

for battery back-up operation with low data retention

current.

PRODUCT FAMILY

KM62V256CL-L

KM62U256CL-L

KM62V256CLE-L

KM62U256CLE-L

KM62V256CLI-L

KM62U256CLI-L

Commercial

(0~70 °C)

Extended

(-25~85 °C)

Industrial

(-40~85 °C)

28-SOP**

28-TSOP(I) R/F

28-SOP**

28-TSOP(I) R/F

28-SOP**

28-TSOP(I) R/F

Power Dissipation

10 µA

10 µA

20 µA

15 µA

20 µA

15 µA

Operating

(Icc2)

PKG Type

Speed

(ns)

Operating

Temp.

Product

List

• Process Technology : 0.7µm CMOS

• Organization : 32K x 8

• Power Supply Voltage

KM62V256C family : 3.3V ± 0.3V

KM62U256C family : 3.0V ± 0.3V

• Low Data Retention Voltage : 2V(Min)

• Three state output and TTL Compatible

• Package Type : JEDEC Standard

28-SOP, 28-TSOP(I)-Forward/Reverse

32Kx8 bit Low Power & Low Vcc CMOS Static RAM

PIN DESCRIPTION

A10

/CS

IO8

IO7

IO6

IO5

IO4

Vss

IO3

IO2

IO1

A0

A1

A2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

/OE

A11

A9

A8

A13

/WE

Vcc

A14

A12

A7

A6

A5

A4

A3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Vcc

/WE

A13

A8

A9

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

A3

A4

A5

A6

A7

A12

A14

Vcc

/WE

A13

A8

A9

A11

/OE

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A2

A1

A0

IO1

IO2

IO3

Vss

IO4

IO5

IO6

IO7

IO8

/CS

A10

28-Pin SOP

28-Pin TSOP

Type I - Forward

28-Pin TSOP

Type I - Reverse

* measured with 30pF test load

** the device with 100ns SOP package in 3.0~3.6V Vcc range is not produced.

FUNCTIONAL BLOCK DIAGRAM

35mA

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Standby

(Isb1, Max)

Vcc Range

3.0~3.6V

2.7~3.3V

3.0~3.6V

2.7~3.3V

3.0~3.6V

2.7~3.3V

70*/100

85*/100

70*/100

85*/100

70*/100

85*/100

I/O1~8

Function

Address Inputs

Write Enable Input

Chip Select Input

Output Enable Input

Data Input/Output

Power

Ground

Y-Decoder

I/O Buffer

Cell Array

A3~A8

A12~14

Pin Name

A0~A14

/WE

/CS

/OE

I/O1~I/O8

Vcc

Vss

/CS, /WE

/OE

A0~2, A9~11