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Z86L97 Datasheet(PDF) 4 Page - Zilog, Inc. |
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4 / 91 page Z86L972/Z86L973/Z86L974 Low-Voltage Microcontrollers PS010504-1002 P R E L I M I N A R Y iv List of Figures Figure 1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. 48-Pin SSOP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 40-Pin DIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Standard Z8 Register File (Working Reg. Groups 0–F, Bank 0) . . . 12 Figure 6. Z8 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. External Interrupt Sources IRQ0–IRQ2 Block Diagram . . . . . . . . . . 16 Figure 9. IRQ Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. General Input/Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 12. Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 13. Active Glitch/Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 14. I-V Characteristics for the Current Sink Pad P43 . . . . . . . . . . . . . . 29 Figure 15. T1 Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 16. Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 17. Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 18. Counter/Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19. Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20. Starting the Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 21. Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 22. Timer Mode Register TOUT Operation . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 23. Counter/Timer Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 24. Internal Clock Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 25. Timer Mode Register TIN Operation . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 26. Prescaler 1 TIN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 27. External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 28. Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 29. Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 30. Counter/Timer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 31. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 32. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 33. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 |
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